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Update on Using Multicore Processors with a Commercial ARINC 653 Implementation

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© Copyright 2017 Wind River. All rights reserved. 1 Update on using multicore processors with a commercial ARINC 653 implementation Paul J. Parkinson Principal Systems Architect Wind River Swindon, United Kingdom Paul.Parkinson@windriver.com Abstract— With the wide availability of multiple core (multi- core) processors, their reduced size, weight and power (SWaP) properties make them extremely attractive for use in Avionics systems. In order to implement a solution on a multi-core platform, the developer will be confronted with numerous implementation and certification obstacles that are not present in uni-core or discrete multiple processor implementations. Achieving safety certification of a multi-core system requires close collaboration between the avionics developers, semiconductor vendors and regulatory agencies. Evolving certification policies and guidance will include both hardware and software aspects of certification. This paper will provide an update of work by Wind River on implementing a COTS ARINC 653 solution for multi-core and provide guidance to the developer on the issues that must be addressed from both a hardware and software perspective in order to understand the potential benefits and certification limitations of multi-core solutions. Keywords—avionics; certification; multicore; I. THE CHALLENGE OF MULTI-CORE CERTIFICATION The introduction of MCP architectures has provided performance gains for enterprise general purpose applications; it has also presented some unique challenges for their use in safety-critical avionics systems. This is because avionics applications have specific requirements, including (but not limited to) application isolation and determinism, and these are not the primary considerations of semiconductor manufacturers when designing MCPs for the commercial market. The avionics industry, academia and certification authorities have undertaken research projects into the use of MCP architectures in avionics applications. A number of researchers have found that there is variation between MCP designs in terms of their suitability for use in avionics applications, due to the impact of architectural design features on application isolation and determinism [1][2]. These relate to factors arising from shared resources on the device, which include use of a single memory controller or shared bus is used by multiple cores (providing a risk of resource contention), and similarly use of separate or shared Level 2 caches per core, as shown in Figure 1. This uncertainty about the selection of multi-core processors for avionics programmes presents a challenge for avionics programmes, and was discussed at length in a previous paper [3]. Fig 1. Notional multi-core cache architecture with shared L2 cache EASA and the FAA have not yet published formal policy / guidance on multi-core certification, which presents a challenge to avionics programmes. However, EASA has published the MULCORS research report [4] and has published the CAST-32 position paper [5], and more recently CAST-32A paper [6], which should be taken into consideration when planning a safety-critical multi-core avionics project in order to reduce certification risk. Programmes may wish to consider the use of a multi-core processor in their next hardware platform even if their current processing requirements do not exceed that provided by a single core, in order to provide adequate processing capacity to meet future processing requirements. The selection of a multi- core processor may also become a necessity due to the lack of availability of single core processors as mentioned earlier. Similarly, some programmes may wish to use multi-core processors which have more than two cores, as 4-core and 8- core devices are now relatively common. The initial CAST-32 paper did not consider multi-core processors with more than two active cores, although the more recent CAST-32A extends the scope to more than two cores. However, certifying multi- core processors will require substantial research and certification leadership to extend the guidance in the MULCORS and CAST-32 papers.

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